USTC/LogicGates

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(NOT Gate)
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[[Image:ustc_not gate.jpg|thumb]]
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[[Image:ustc_not_truth table.jpg]]
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The NOT gate or inverter is a digital logic gate that implements logical negation. It behaves according to the truth table to the right. A HIGH output (1) results if the inputs is LOW (0). If the input is HIGH (1), a LOW output (0) results.
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(cited from wikipedia.com)
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The NOT gate is a digital logic gate that implements logical negation. It behaves according to the truth table to the left. A HIGH output (1) results if the inputs is LOW (0). If the input is HIGH (1), a LOW output (0) results.(cited from wikipedia.com)
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The draft to the right shows the NOT gate we design in the project.

Revision as of 05:30, 2 August 2007

NOR Gate

Ustc nor gate.jpg

Ustc nor truth table.jpg


The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0). If one or both input is HIGH (1), a LOW output (0) results.

p NOR q is only true when both p and q are false.

The NOR operation is a logical operation on two logical values, typically the values of two propositions, that produces a value of true if and only if both operands are false. In other words, it produces a value of false if and only if at least one operand is true.







NAND Gate

Ustc nand gate.jpg

Ustc nand truth table.jpg The NAND operation is a logical operation on two logical values, typically the values of two propositions, that produces a value of false if and only if both of its operands are true. In other words, it produces a value of true if and only if at least one of its operands is false.

A LOW output results only if both the inputs to the gate are HIGH. If one or both inputs are LOW, a HIGH output results.












NOT Gate

Ustc not gate.jpg

Ustc not truth table.jpg

The NOT gate is a digital logic gate that implements logical negation. It behaves according to the truth table to the left. A HIGH output (1) results if the inputs is LOW (0). If the input is HIGH (1), a LOW output (0) results.(cited from wikipedia.com) The draft to the right shows the NOT gate we design in the project.