http://2007.igem.org/wiki/index.php?title=USTC/a_half_adder&feed=atom&action=historyUSTC/a half adder - Revision history2024-03-28T20:10:50ZRevision history for this page on the wikiMediaWiki 1.16.5http://2007.igem.org/wiki/index.php?title=USTC/a_half_adder&diff=12425&oldid=prevZhao Yun at 08:04, 1 August 20072007-08-01T08:04:33Z<p></p>
<p><b>New page</b></p><div>Our main design is about a Half Adder. The so-called half adder comprises two one-bit inputs and two one-bit outputs. Inside a half adder are two core devices: an XOR Gate and an AND Gate the output of which are respectively the Sum and Carry of the two inputs. The following is a truth table of a Half Adder. <br />
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[[Image:.jpg]]</div>Zhao Yun