USTC/a half adder

From 2007.igem.org

Our main design is about a Half Adder. The so-called half adder comprises two one-bit inputs and two one-bit outputs. Inside a half adder are two core devices: an XOR Gate and an AND Gate the output of which are respectively the Sum and Carry of the two inputs. The following is a truth table of a Half Adder.


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