Revision as of 14:03, 26 October 2007

Introduction Team Members Acknowledgments Site map

Introduction Model Overview Detailed Model Final Model Modeling Basics Page Mathematical Model FSM View Page Flip-Flop View Page Parameters Page

Introduction Test Cases Sensitivity Analysis

Introduction The Complete System System Phases System Parts Page Lab Notes Page

The ETH Zurich 07 Team Team Description Brainstorming Page

An Engineer's View on Biological Learning

Fig. 1: Schematic view on the system implemented by logical gates.

An equivalent system behavior can be realized using flip-flops, implemented by logical gates:

As already shown in the finite state machine representation (FSM), the proposed system consists of three different states and recognizes four different inputs. In total, this adds up to twelve different transitions. In order to implement these twelve transitions with a digital system, at least four binary inputs are required (allowing for a maximum of 16 transitions) and since the proposed system has four different outputs, at least two binary outputs are required. Here, we chose an implementation using two JK flip-flops consisting of NAND gates. An overview of the resulting system is given in Fig. 1 and details concerning flip-flop and NAND gate behavior are given in the following table:

J	K	Q_next	A	B	A NAND B
0	0	Q_prev	0	0	1
0	1	0	0	1	1
1	0	1	1	0	1
1	1	¬Q_prev	1	1	0

When initializing the system we set both outputs Q to zero. The mapping from inputs ( AHL+IPTG, IPTG, AHL+aTc, aTc) and system states ( q₀, q₁, q₂) to the binary inputs (J₁, K₁, J₂, K₂) is given by following table:

states/inputs	AHL+IPTG	IPTG	AHL+aTc	aTc
q₀	J₁=0, K₁=1, J₂=1, K₂=0	J₁=0, K₁=0, J₂=0, K₂=1	J₁=1, K₁=0, J₂=0, K₂=1	J₁=0, K₁=1, J₂=0, K₂=1
q₁	J₁=0, K₁=1, J₂=1, K₂=0	J₁=0, K₁=0, J₂=0, K₂=1	J₁=0, K₁=1, J₂=0, K₂=0	J₁=0, K₁=0, J₂=1, K₂=1
q₂	J₁=1, K₁=0, J₂=0, K₂=0	J₁=1, K₁=1, J₂=0, K₂=0	J₁=1, K₁=0, J₂=0, K₂=1	J₁=0, K₁=1, J₂=0, K₂=1

Here, we assume that the FSM system states q₀, q₁, q₂ are mapped to the outputs Q₁ and Q₂ as follows:

FSM states/output coding	Q₁	Q₂
q₀	0	0
q₀	0	1
q₀	1	0

The final mapping from transitions to the biological reporters is then given by:

J₁=0, K₁=1, J₂=1, K₂=0	J₁=0, K₁=0, J₂=0, K₂=1	J₁=1, K₁=0, J₂=0, K₂=1	J₁=0, K₁=1, J₂=0, K₂=1	J₁=0, K₁=1, J₂=1, K₂=0	J₁=0, K₁=0, J₂=0, K₂=1	J₁=0, K₁=1, J₂=0, K₂=0	J₁=0, K₁=0, J₂=1, K₂=1	J₁=1, K₁=0, J₂=0, K₂=0	J₁=1, K₁=1, J₂=0, K₂=0	J₁=1, K₁=0, J₂=0, K₂=1	J₁=0, K₁=1, J₂=0, K₂=1
cyan	cyan	red	cyan	cyan	cyan	yellow	green	cyan	cyan	cyan	yellow

@@ Line 89: / Line 89: @@
 An equivalent system behavior can be realized using [http://en.wikipedia.org/wiki/Flip-flop_%28electronics%29 flip-flops], implemented by [http://en.wikipedia.org/wiki/Logic_gate logical gates]:
-As already shown in the [https://2007.igem.org/ETHZ/FSM finite state machine representation] (FSM), the proposed system consists of three different states and recognizes four different inputs. In total, this adds up to twelve different transitions. In order to implement these twelve transitions with a digital system, at least four binary inputs are required (allowing for a maximum of 16 transitions) and since the proposed system has four different outputs, at least two binary outputs are required. Here, we chose an implementation using two JK flip-flops consisting of [http://en.wikipedia.org/wiki/Nand_gate#NAND_gate NAND gates]. An overview of the resulting system is given in Fig. 1 and details concerning flip-flop and NAND gate behavior are given in the following table:
+As already shown in the [[ETHZ/FSM | finite state machine representation]] (FSM), the proposed system consists of three different states and recognizes four different inputs. In total, this adds up to twelve different transitions. In order to implement these twelve transitions with a digital system, at least four binary inputs are required (allowing for a maximum of 16 transitions) and since the proposed system has four different outputs, at least two binary outputs are required. Here, we chose an implementation using two JK flip-flops consisting of [http://en.wikipedia.org/wiki/Nand_gate#NAND_gate NAND gates]. An overview of the resulting system is given in Fig. 1 and details concerning flip-flop and NAND gate behavior are given in the following table:
 {|  class="wikitable" border="1" cellspacing="0" cellpadding="2" style="text-align:left; margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse;"
@@ Line 103: / Line 103: @@
 |}
-When initializing the system we set both outputs ''Q'' to zero. The mapping from inputs ([https://2007.igem.org/ETHZ/FSM AHL+IPTG, IPTG, AHL+aTc, aTc]) and system states ([https://2007.igem.org/ETHZ/FSM ''q''<sub>0</sub>, ''q''<sub>1</sub>, ''q''<sub>2</sub>]) to the binary inputs (J<sub>1</sub>, K<sub>1</sub>, J<sub>2</sub>, K<sub>2</sub>) is given by following table:
+When initializing the system we set both outputs ''Q'' to zero. The mapping from inputs ([[ETHZ/FSM | AHL+IPTG, IPTG, AHL+aTc, aTc]]) and system states ([[ETHZ/FSM | ''q''<sub>0</sub>, ''q''<sub>1</sub>, ''q''<sub>2</sub>]]) to the binary inputs (J<sub>1</sub>, K<sub>1</sub>, J<sub>2</sub>, K<sub>2</sub>) is given by following table:
 {|  class="wikitable" border="1" cellspacing="0" cellpadding="2" style="text-align:left; margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse;"
@@ Line 127: / Line 127: @@
 |}
-Here, we assume that the FSM system states ''q''<sub>0</sub>, ''q''<sub>1</sub>, ''q''<sub>2</sub> are mapped to the outputs ''Q''<sub>1</sub> and ''Q''<sub>2</sub> as follows:
+Here, we assume that the [[ETHZ/FSM | FSM system states]] ''q''<sub>0</sub>, ''q''<sub>1</sub>, ''q''<sub>2</sub> are mapped to the outputs ''Q''<sub>1</sub> and ''Q''<sub>2</sub> as follows:
 {|  class="wikitable" border="1" cellspacing="0" cellpadding="2" style="text-align:left; margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse;"

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Revision as of 14:03, 26 October 2007

An Engineer's View on Biological Learning